Basic HTML Version
A) Video up, address decode, program RAM and ROM
The Vidiot module uses a high performance S bit microprocessor the MC6S09 as its video uP US. This uP provides
many 16 bit operations and
a
compact orthogonal instruction set with versatile addressing
==
that maximizes
the program performance. A bus cycle begins on the MC6809 with the address and R/W lines changing to a known
state. Shortly after they are stable the
Q
(quadrature) clock output goes high. One quarter of a bus cycle later
the
E
(enable) clock output goes high. The addressed device on the bus places its data on 00-07 (R/W high)
or takes its data from 00-07 (R/W low) during the
E
clock. The bus cycle terminates when
E
goes low.
Addresses are decoded by U15 to determine which bus device the MC6809 is accessing. This is a dual 2 to 4 line
decoder and the high-order address line A 15 is used to enable one half or the other. When A 15 is high the program
ROMs U9, U10, U11 or U12 are selected. If A15 is low the interface circuitry, PIA U7, VOP U16 or program RAM
U13 and U14 are selected. Both halfs of the decoder U15 are enabled by the E clock from U8 to time the data
transfer on the bus.
The program RAM is provided by U13 and U14. These are 1K x 4 NMOS static RAM. The data bus 00-07 is
split in half with 00-03 connected to U13 and 04-07 connected to U14. Both parts are selected by the decoder
at the same time and the R/w line from U8 is used to perform a read cycle (R/W high) or a write cycle (R/W low).
The program ROM is provided by U9, U10, U11 and U12. These 29 pin sites may be configured to accept2K, 4KorSK
ROMs giving a maximum of 32K of video program storage.
B) Communication Interface
The interface sub-section consists of U1, U2, U3, U4, U6 and U7. These parts work with the video uP U8 to pro-
vide MPU-Vidiot communication, Vidiot switch reading, and video-sound uP communication. The MPU-Vidiot com-
munication was explained under NORMAL OPERATION above and will not be detailed here. The switch reading is
performed by U7 which provides four switch strobes and eight switch returns that operate similar to the MPU
switch read. The video sound communication uses the low order four switch returns of U7 and a strobe line. The
information is passed as two half-bytes (nybbles) over these four lines one per edge of the strobe (CB2). The current
timing for this process is shown below.
+-----------
+ + -----------
+
PBO-PB3------+
1st nybble
+ + +
2nd nybble
+------
+ -----------
+ + -----------
+
f- 9 usec
--1
f- 30 usec
C~
+--------------+
I
I
-------------+
+------------
C) Video Display Processor, Video RAM, Video Amp Dematrix
The heart of the Vidiot module is the VOP U16. This LSI chip provides high resolution video capability. The VOP
provides all necessary video, control and synchronization signals and also controls the storage, retrieval and refresh
of data in the dynamic screen memory (VRAM). It provides a 256 x 192 pixel pattern display in 15 colors and 32
object oriented patterns (sprites) that may be easily and smoothly moved with a minimum number of data operations.
The video uP U8 communicates with the VOP over its data bus with three control lines. With this interface the uP can
read or write to the VRAM, write to the VOP control registers and read the VOP state. The VOP interrupts the uP
at the end of each raster scan to allow the uP to update the VRAM during the blank screen vertical interval.
The screen image is generated from data stored in the VRAM. The VRAM is connected to the VOP with two 8 bit
buses and three control lines. The RAMs U19 through U26 form an array of 16384 x 8 bits of memory. The dynamic
memories use a multiplexed address/data bus. First the row address is output by the VOP and the RAS signal is
issued. Next the column address is output followed by CAS. The data is read in when VOP R/W is high or written
when R/W is low. The dynamic memories require periodic refreshing of their contents to keep it intact. The VOP
uses a RAS only cycle to refresh the RAMs.
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