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J) 10th Flash
The last test attempts to verity that the VRAM is operational. The uP tells the VDP the RAM type and size a..
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allows it to start the dynamic RAM refresh operation. It then attempts to store and verity an incrementing pattern
that is not address aligned in all 16384 locations. If this succeeds the test is repeated with a decrementing pattern.
When all tests
are
completed the uP flashes the LED and proceeds to initialize the Vidiot for game play.
K) Vidiot Initialization
The Video uP initializes the PIA for MPU-Vidiot communications.
Video Joystick switch reading and Sound uP
communications.
It clears the scratch RAM and sets up the initial Video variables. It configures the VDP and its
VRAM parameter tables then awaits game play instructions from the MPU. No screen is displayed unless instruc-
tions are received from the
M
Pu.
II. NORMAL OPERATION
The Vidiot serves three functions. First it is a display device for the MPU. Second it is a sound system for the
MPU. And lastly it is a video game board. The Vidiot and MPU work together to provide an integrated Video game
with a Pinball feature. Their combined operation requires coordinated inter-uP communication. This communication
is provided by the interface on the' Vidiot module. Interface Data and Status is returned to the MPU on its switch
return lines. The MPU controls this information flow by selectively enabling the Video Output or Status Data drivers
synchronously with its switch reading. To send a byte of information to the MPU the video uP latches the data
into U1 and sets a status bit indicating data is available. When the MPU polls the Vidiot Status Data it detects the data
available and subsequently reads the data by enabling the U1 output drivers. The process of reading the data
generates an interrupt to the video uP which causes it to clear the data available status bit. To send a byte of
information to the Vidiot the MPU latches the data into U2. The process of latching the data generates an interrupt
to the video uP which causes it to set a status bit indicating the port is unavailable for writing. After the video uP
reads the data byte it clears the status bit indicating more data may now be sent.
III. POWER SUPPLIES
The Vidiot requires +12vdc
@
4A unregulated voltage for its operation. All board voltages are derived from this
source. The video uP and its circuitry require
+svcc.
which is generated from this unregulated input by VR1,
CR1. CR2. CR3. C50. C51. C52 and C53. The sound uP and its circuitry also require +5vdc. which is generated
by VR2. C56. C57, C58 and C59. The Video Amp Dematrix section requires +8.2vdc, which is generated by VR4.
R106 and C89. The Self-Test indicator. Low pass filter and Power Amp require +tzvdc unregulated which is
obtained from the + 12vdc input to the module. This unregulated voltage is filtered for ESD protection before
being used by any power supply by L1, C41, C43 and C44.
IV. RESET CIRCUIT
On power-up the uP chips require that +5v
+I>:
.25v DC be applied for 100 milliseconds before their RESET
lines are allowed to swing from
°
to 4.8v. The RESET circuit on the Vidiot module works with the unregulated
voltage to the regulator VR1 to prevent the REST line from going high until the +5v supply has had time to stabilize
after power on. Zener diode VR3 and transistors 04 and 05 with R66 through R71 form a Valid Power Detector circuit
that monitors the input voltage to VR1. This regulator requires a minimum of +7.5v input before it provides a
+5v output. When this condition has been met diode CR6 allows COO to charge through R63. This RC time con-
stant provides the initial 100 MSEC delay to allow the uP oscillators to stabilize. The voltage across C90 is monitored
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by
02, 03,
CR4. CR5 and RS7 through R62. When it has reached about +2.Sv the RESET
line
snaps high to allow
the uPs to start program execution. In the event that the input to VR1 drops below +7.5v for an instant the Valid Power
Detector quickly discharges COOthrough R64 and CR6 to re-prime the RC time constant and insure a correct RESET
cycle when power is re-applied.
This RESET signal is applied to the video uP U8, the video PIA U7, the VDP U16 and the sound uP U27. It is also
used to set the mode of operation for the sound uP U27 via 06, Rn, CR7 and CR8. This circuitry forces a 010 code
on P20, P21 and P22 of the sound uP during RESET which causes the sound uP to come up in an internal RAM,
external ROM, multiplexed address/data mode.
V. VIDEO SECTION
The Vidiot module video section is made up of three sub-sections. The video uP, its address decoder, program RAM
and program ROM form one section. The communication interface forms another sub-section, and the Video Display
Processor. Video RAM and Video Amp Dematrix the last sub-section.
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