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The TMS9928ANL VDP outputs color difference signals, luminance (Y), red minus luminance (R-Y) and blue minus
luminance
IB-Y). The synchronizing information for the raster timing is contained in the Y output. These outputs
have to be converted to red (R), green (G), blue (8) and SYNC signals for the color monitor. The Video Amp
Dematrix does this and amplifies the signals to the levels required by the monitor. Operational amplifiers U17 and
U18 are high-speed current-mirror circuits. The Y and R-Y signals are summed at the plus input to U17 by R91
and R93 and amplified. These signals also contain a DC offset voltage that must be removed. Potentiometer RT3
and R98 inject an adjustable current into the minus input of U17 which removes this offset and allows the red
level to be adjusted. Likewise the Y and 8-Y signals are summed in another section of U17 by R84 and R85 and
amplified. Potentiometer RT1 and ROOact to remove the DC offset and allow blue level adjustment. The R-Y and
8-Y signals have encoded in them a G-Y component. Resistors R8S and R92 sum this component and present
it to the minus ;nputof U18 where
it.has
the Y component added via R100. Potentiometer RT4 and R103 remove the
DC offset and allow the green level to be adjusted. The synchronization information in the Y output is obtained by
detecting the lowest levels of this signal. The other half of U18 forms a comparator which compares the Y signal level
against a reference provided by RT2 and R94. When the Y Signal goes below the reference level the output of U18
goes low providing a negative going SYNC signal for the monitor.
VI. SOUND SECTION
The sound section of the Vidiot module consists of two sub-sections. The sound uP, its bus demultiplexor. address
decoder and program ROM form one section. The D to A converter, low pass filter and power amplifier form the other.
A) Sound uP, bus demux, address decode and program ROM
The Vidiot module uses a single chip microcomputer the MCS803 as its sound uP U27. This uP provides two I/O ports,
128 bytes of RAM, a multifunction timer and external ROM capability. A bus cycle begins on the MC6803 with
the address/data and R/W lines changing to a known state. Shortly after they are stable the AS (address strobe)
clock is output This is used to latch the low order address lines AD-A7 from the ADD-AD7 bus via U28. After AS
goes low the ADO-AD7 lines become the DD-D7 data bus. One half of a bus cycle later the
E
(enable) clock output
goes high. The addressed device on the bus places its data on ADO-AD7 (R/W high) or takes its data from ADO-AD7
(R/W low) during the E clock. The bus cycle terminates when E goes low.
Addresses are decoded by U31 to determine which external bus device the MC6803 is accessing. Address line A 15
must be high to address the program ROMs U29 and U30. Address line A14 determines which ROM is selected.
When A14 is high U29 is selected. When A14 is low U30 is selected. The
E
clock is used to qualify the decoding to
time the data transfer and remove the ROMs from the ADO-AD7 bus for low order address latching into U28.
The program ROM is provided by U29 and U30. These 28 pin sites may be jumpered to accept 2K, 4K or 8K ROMs
giving a maximum of 16K of sound program storage.
8) 0 to A, low pass filter and power amplifier
Sounds are generated by waveform synthesis using a D to A converter. The converter is supplied with 8 bit data
from one of the MC6803 I/O ports P1D-P17. The uP actually constructs waveforms by controlling the D to A. The
D to A converter is a low-cost single-supply part with a voltage output that is proportional to the binary input code
and the reference voltage input. A 2.Svdc reference with a low slope resistance is developed by Q7, R79, R80,
R81 and C92. The 0 to A output voltage varies from 2.Svdc with an input of 11111111 to Ovdc with an input
of 00000000.
The constructed waveform contains unwanted frequency components due to its formation. These are removed by a
fifth-order Butterworth response low pass filter. The filter is formed by U33, R109 R118, C102 C106. The output
of the filter is developed across RT5 which allows the volume to be adjusted.
The adjusted signal level is fed to the power amplifier U34 via C112. Device U34 is an 8 watt power amplifier. Network
C107, R120 and R121 form a feed-back circuit that sets the gain of the amplifier to 40db. Network C108 and R119
rolloff the high frequency response of the amplifier to provide stability and minimize noise. Caoacitor C109 couples
the signal to the speaker while blocking the DC component and R122 and C110 form a high frequency shunt to
suppress bottomside signal oscillation.
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