Basic HTML Version
The TMS9928AN L VDP outputs color difference signals, luminance (Y), red minus luminance (R - Y) and blue minus
luminance (S-Y). The synchronizing information for the raster timing is contained in the Y output. These outputs
have to be converted to red (R), green (G), blue (6) and SYNC signals for the color monitor. The Video Amp
Oematrix does this and amplifies the signals to the levels required by the monitor. Operational amplifiers U17 and
U18 are high~speed current-mirror circuits. The Yand R-Y signals are summed at the plus input to U17 by R91
and R93 and amplified. These signals also contain a DC offset voltage that must be removed. Potentiometer RT3
and R98 inject an adjustable current into the minus input of U17 which removes this offset and allows the red
level to be adjusted. Likewise the Y and 8-Y signals are summed in another section of U17 by R84 and R85 and
amplified; Potentiometer RTl and ROOact to remove the DC offset and allow blue leve! adjustment. The R-Y and
8-Y signals have encoded in them a G-Y component. Resistors R86 and R92 sum this component and present
It to the minus input of U18 where it has the Y component added via R100. Potentiometer RT4 and R 103 remove the
DC
offset and allow the green level to be adjusted. The synchronization information in the Y output is obtained by
jetecting the lowest levels of this signal. The other halt of U18 forms a comparator which compares the Y signal level
igai nst a reference provided by RT2 and R94. When the Y sig nal goes be low the reference level the output of U18
~s low providing a negative going SYNC signal for the monitor.
VI. SOUND SECTION
The sound section of the Vidiot module consists of two sub-sections. The sound uP, its bus demultiplexor, address
decoder and program ROM form one section. The D to A converter, low pass filter and power amplifier form the other.
A) Sound uP, bus demux, address decode and program ROM
The Vid iot module uses a single eh ip microcomputer the MC6803 as its sound uP U27. Th is uP provides two
110
ports.
128 bytes of RAM. a multifunction timer and external ROM capability. A bus cycle begins on the MC6803 with
the address/data and R/W lines changing to a known state. Shortly after they are stable the AS (address strobe)
clock is output. This is used to latch the low order address lines AO-A7 from me ADO-AD7 bus via U28. After AS
goes low the ADo-AD7lines become the 00-07 data bus. One half of a bus cycle later the E (enable) clock output
goes high. The addressed device on the bus places its data on ADO-AD7 (RfW high) or takes its data from ADO-A07
IRIW low) during the E clock. The bus cycle terminates when E goes low.
.•
Mdresses are decoded by U31 to determ ine which external bus device the MC6803 is accessing. Address line A 15
must be high to address the program ROMs U29 and U30. Address line A14 determines which ROM is selected.
When A, 4 is hig h U29 is selected. When A' 4 is low U30 is selected. The E clock is used to Qual ify the decod ing to
time the data transfer and remove the ROMs from the ADO-AD7 bus for low order address latching into U28.
Ihe program ROM is provided by U29 and U30. These 28 pin sites may be iurnpered to accept 2K, 4K or 8K ROMs
giving a maximum of 16K of sound program storage.
B) D
to
A. low pass filter and power amplifier
Sounds are generated by waveform synthesis using a D to A converter. The converter is supplied with 8 bit data
rom one of the MC6803
1/0
ports PlO-P17. The uP actually constructs waveforms by controlling the D to A. The
D
to A converter is a low-cost single-supply part with a voltage output that is proportional to the binary input code
md the reference voltage input A 2.5vdc reference with a low slope resistance is developed by Q7, R79, RBO,
~B1
and C92. The D to A output voltage varies from 2.5vdc with an input of 11111111 to Ovdc with an input
)f 00000000.
the constructed waveform contains unwanted frequency components due to its formation. These are removed by a
ifth-order Butterworth response low pass filter. The fi Iter is formed by U33, R109 R118, C102 C106. The output
(If the filter is developed across RT5 which allows the volume to be adjusted.
the adjusted signal level is fed to the power amplifier U34 via C112. Device U34 is an 8 watt power amplifier. Network
: 107. R120 and R121 form a feed-back circu it that sets the gai n of the ampi ifier to 40d b. Network Cl 08 and R119
roUoff the high frequency response of the amplifier to provide stability and minimize noise. Capacitor C109 couples
Jhe Signal to the speaker wh iIe blocking the DC component and R122 and C110 form a h igh frequency shu nt to
suppress bottomside Signal oscillation.
30
1
1
{
r
j
.1:
r
I
iL._
,
,
r
,